110V Low Clamp DC Bus Protection Device

Part 1: Industry Pain Points (110V Bus DC-DC Power Supply)**

1. Narrow Chip Voltage Window, System Transient is "Hard"

In 110V-level bus systems, the absolute maximum voltage rating of many DC-DC/power management ICs on the market is concentrated at 150V. This means that during surges, hot-plugging, or harness-induced spikes, the input protection must tightly clamp the chip pin voltage within a safe window close to but not exceeding 150V. Traditional TVS devices often exhibit high clamping voltage under large currents, causing the chip terminal voltage to potentially exceed the window, leading to latent damage or immediate failure.

2. "More Fragile" Characteristics Due to Process Evolution

As power IC processes evolve toward smaller line widths and higher integration, the margins of gate oxide, drift region, and internal protection structures are further compressed. Meanwhile, chips often integrate more high-voltage switching devices and control circuits. Any abnormal input spike can trigger: gate oxide stress accumulation, ESD/surge protection structure breakdown or leakage increase, internal parasitic structure conduction due to overvoltage causing localized overheating, and parameter drift from repeated transients, resulting in "functional but unreliable" latent failures.

3. System-Level Challenges: Harness, Inductance, and Switching Noise Superposition

110V buses are often accompanied by long harnesses, large loop inductance, and high di/dt from power-stage high-speed switching. During hot-plugging, load transients, relay switching, or external surge coupling, spike energy is concentrated at the input. If the protection device's clamping voltage is not low enough or the response path is not short enough, the spike directly reaches the chip pin.

Part 2: Our Device Solution**

The design goal of the NR5.0SMDJ110CA is not to "absorb all surge energy," but to: within the system's acceptable energy range, clamp the voltage as low and stable as possible, providing a larger safety margin for 150V-rated DC-DC/power ICs.

VC1 VC2 VC1 VC2 VC1 VC2 VC1 VC2

139.8V 140.3V 141.7V 142.5V 144.0V 144.6V 146.0V 146.6V

IPP1 IPP2 IPP1 IPP2 IPP1 IPP2 IPP1 IPP2

28.36A 28.38A 31.17A 31.18A 33.97A 33.98A 36.75A 36.76A

4. Conventional Electrical Test Parameters

VBR1: 130V, VBR2: 130V, VBR1: 130V, VBR2: 130V, VBR1: 130V, VBR2: 130V

IR1: 0.000uA, IR2: 0.051uA, IR1: 0.025uA, IR2: 0.000uA, IR1: 0.072uA, IR2: 0.000uA

5.1.2/50us & 8/20us Surge Capability Test

Surge Voltage

Vc@Ippmax V | Ippmax A | Vc@Ippmax V | Ippmax A | Vc@Ippmax V | Ippmax A

0.8KV: 140V, 288A | 142V, 296A | 144V, 296A

0.9KV: 142V, 226A | 142V, 344A | 146V, 336A

1.0KV: 144V, 392A | 144V, 384A | 146V, 384A

1.1KV: 146V, 432A | 146V, 432A | 146V, 432A

1.2KV: 148V, 472A | 146V, 480A | 146V, 462A

Design Focus: Low Clamping + Verifiable Surge Capture

Under 1.2/50μs & 8/20μs surge conditions, test capture shows that under 0.8–1.2kV impact, Vc@Ippmax of this device falls approximately in the 140–148V range (samples 2/3/4). In routine electrical testing, VBR is approximately 130V grade, and device capacitance test sample is about 876.671pF.

System Implementation Recommendations (Principles)**

1. Place the TVS as close as possible to the input pin and return ground of the protected chip, with short traces and a small loop.

2. Between the TVS and the bus, a small resistor/ferrite bead/fuse can be used to achieve energy limiting and graded protection (selected based on system loss tolerance).

3. For long wire harness applications, it is recommended to add a "coarse protection" stage at the interface side, and use this device for "precision clamping" near the chip on the board.

Part 3: Application Scenarios and Advantages**

3.1 Typical Application Scenarios**

This low-clamping TVS device is designed for 110V DC bus systems and is suitable for DC-DC input protection scenarios requiring high power supply reliability.

In power architectures, it can be used for protecting the input of DC-DC power supplies with a chip withstand voltage rating of 150V, reducing the direct impact of surges and transient spikes on the power chip. In industrial power supplies and two-wheeled/three-wheeled electric vehicle systems, it can be applied for front-end protection between the high-voltage battery pack and the DC-DC module. In control systems for motor drives, fans, pumps, and compressors, it is suitable for surge suppression and stability enhancement at the auxiliary power input.

Furthermore, in energy storage and photovoltaic systems, this solution is also well-suited for bus input protection scenarios in the 100V to 120V range, but system evaluation and device selection must be performed based on the actual surge level.

3.2 Performance Comparison with Traditional TVS Solutions**

In traditional designs, TVS devices primarily aim to absorb surge energy. However, in practical applications, precise protection of the power chip's withstand voltage window is more critical. The low-clamping design offers significant advantages in this regard.

3.3 Selection and Usage Recommendations**

During system selection, it is recommended to prioritize applications in power architectures with a "nominal bus voltage of 110V and chip withstand voltage of 150V" to achieve a reasonable match between clamping voltage and device withstand voltage window.

For environments with higher surge levels or repeated impacts, board-level testing should be conducted to verify device capability and evaluate design margin, ensuring long-term system reliability.

In PCB layout, priority should be given to ensuring a short, low-impedance, and direct return path for the TVS device, avoiding long common ground paths with high-current switching loops to minimize the impact of parasitic parameters on protection effectiveness. Additionally, for long wire harness or high-inductance loop systems, a graded protection strategy at the interface side and chip side is recommended to further enhance overall surge immunity.

Part 4: Conclusion**

The NR5.0SMDJ110CA is designed for 110V bus power systems, focusing on "protecting power chips with a 150V withstand voltage window." Through a lower clamping strategy, it reduces the clamping voltage to approximately 140–148V range (test capture) under typical surge conditions, helping customers reduce input overvoltage stress and minimize the risk of latent failure. It is recommended to optimize based on the system surge level and layout return path to achieve "verifiable and reproducible" protection effects.